The present invention relates to data processing systems, and more particularly to modular systems comprised of multiple processors which are arranged hierarchically and characterized by substantially identical bus structures.
The proliferation of personal computer type data processing systems utilizing a limited class of microprocessor models has created a secondary market involving printed circuit board level products which provide new or extended features at relatively nominal costs. The architecture of such conventional personal computer systems facilitates the usage of secondary market products through the presence of a master or system bus shared not only by the master microprocessor, master memory, and input/output, but also by any peripheral devices connected to the bus, including but not limited to co-processors, communication controllers, and disk controllers. Management of all the devices connected to the master bus is under the control of the microprocessor, which itself is responsive to the operations defined by software whether resident in the microprocessor in the form of microcode or resident in bus addressable memory.
The variety of the products directly connectable to the master bus continues to expand both in feature diversity and performance. Unfortunately, even intelligent peripherals attached to the master bus require significant intervals of microprocessor operating time to exercise the additional functions. Though the recent advent of "smart" peripherals has reduced the number and types of operations performed by the master microprocessor, such gains are often offset by increases in the number of peripherals on the master bus. The effect of using single master bus architecture as the peripheral count increases is to reduce the effective data processing rate of the personal computer system.
The conventional industry response to such degradations of the personal computer data processing speed has been to increase the microprocessor speed, with the undesired effect of requiring higher speed RAM or cashe memory architectures, or to elevate the intelligence of the peripherals, in the sense of making "smart" printed circuit board type peripheral products. Nevertheless, the shared use of the master bus by an increasing count of peripherals will continue to burden the master microprocessor.
One approach to the problem of maintaining processor speed in the face of additional peripherals is disclosed in U.S. Pat. No. 4,484,273. According to that teaching, the common computer system bus is supplemented by two additional bus systems. The first of the supplemental buses is shared by a multiplicity of processor devices and interfaces to the common system bus. The second supplemental bus is shared by multiple memories and peripheral units, likewise connected to the common system bus through multiple interfaces. Though the data processing capability of such a system is elevated, the unique architecture and software to implement the memory sharing, interface operations and processor executive control functions are incompatible with prevailing personal computers architecture standards.
An architecture somewhat more similar to the present invention appears in the TMS 9650 Multiprocessor Interface (MBIF) Data Manual recently published by Texas Instruments Corporation in support of the TMS 9650 product. According to that master system bus which is shared by the host/master processor and the main memory. All slave buses are connected through the TMS 9650. Each slave bus includes individual microprocessor, memory and input/output functional blocks, so that the TMS 9650 performs the operations of an intelligent peripheral controller. Although main memory direct access is a contemplated variant of the architecture, there is no simultaneous sharing of memory between the master system bus and the slave bus suitable to make the slave bus an autonomous master bus for a next successive level in the architecture.
Consequently, there exists a need for a computer system architecture in which the buses are suitable for hierarchical configuration without defined limits in the context of a standardized circuit board type product. When operated in a master-slave mode, the architecture must provide a bus structure and operating system environment in which the master bus can control a multiplicity of slave peripherals which are themselves each masters of a hierarchically distinct level of bus.